Please note - Version 1.2 has been released here: PhaseLatch v1.2 - 20MSPS ADC
v1 clearance: The RAM chip is omitted from this revision, so the remaining v1 boards are discounted. For SDR use with a separate FX2LP USB streaming board, ADC samples stream directly to the computer, so RAM on the PhaseLatch board is not needed for that setup. The FX2LP board is not included.
PhaseLatch is an experimental, open-source ADC board designed to interface directly with classic MOS 6502-class CPUs. The board features a dual-channel, 10-bit, 20 MSPS analog-to-digital converter with straight binary parallel output, allowing ADC data to be memory-mapped directly onto a 6502 data bus.
Unlike typical SDR front-ends that rely on modern microcontrollers or FPGAs, PhaseLatch intentionally targets highly constrained 8-bit systems. This makes it ideal for exploring bus timing, external memory expansion, and minimalist DSP techniques such as Goertzel tone detection running entirely on the CPU.
The board uses an Arduino-shield-style form factor and is designed to stack with the PhaseLoom IQ mixer and the 65uino system, enabling modular SDR experiments and retro-computing projects. While the ADC itself supports high sample rates, achievable throughput depends on CPU speed and software design.
PhaseLatch is intended for experimentation, learning, and pushing vintage hardware beyond its original limits.
HW Source: https://github.com/AndersBNielsen/PhaseLatch
Software is part of the 65uino