Retro computing field guide · Part 3

How a 74HC245 shares an 8-bit bus

The 74HC245 is a gatekeeper for eight data wires. It can pass data in either direction—or disconnect both sides so another chip can use the bus.

See the MC74HC245AN

Why put a chip between two buses?

On a simple computer, several devices may connect to shared data wires. If two active outputs drive different values at once, they fight. The 74HC245 is an 8-bit bidirectional bus transceiver: its A1–A8 pins face one bus, and B1–B8 face another. Each A pin pairs with the same-numbered B pin. It does not store a byte or decide which address is selected; control logic tells it when to pass data.

Two eight-wire buses with a 74HC245 between them; enabled direction high passes A to B, direction low passes B to A, disabled isolates both
Direction chooses which side drives the other. Output enable decides whether the chip drives either side at all.

Two control inputs, three states

/OE high: disconnected

The outputs are high impedance, often written Hi-Z. That means the chip is electrically quiet on both buses—not that it sends a logic 0.

/OE low, DIR high: A → B

Whatever logic levels appear on A1–A8 are reproduced on B1–B8. The A side is read as input and the B side is driven.

/OE low, DIR low: B → A

Data travels the other way. The B side is read as input and the A side is driven.

The slash in /OE means active low: a low level enables the outputs. DIR is not active-low; high means A to B. The eight channels are non-inverting, so a 1 remains a 1.

Find the pins

Top-view 20-pin DIP pinout: DIR pin 1, A1 to A8 pins 2 to 9, ground pin 10, B8 to B1 pins 11 to 18, output enable pin 19, VCC pin 20
Top view of the through-hole 20-pin package, notch at the pin-1 end. Pin numbers and function table follow the manufacturer datasheet.

A concrete read example

  1. Suppose a selected ROM is on bus B and the CPU is on bus A. The address decoder selects the ROM for a read.
  2. Control logic sets DIR low, so data may travel from B to A, and brings /OE low only when the ROM is ready to drive the bus.
  3. The byte crosses the 74HC245 to the CPU. When that transaction ends, /OE goes high again, isolating the buses.
Not a drop-in bus fix. A 74HC245 does not generate correct read/write timing or chip selects for you. Never let another device drive the destination bus at the same time. Keep control inputs at defined levels, add a nearby 0.1 µF supply bypass capacitor, and check supply voltage, logic thresholds, fan-out and timing for the exact parts in your circuit. HC input thresholds are not automatically suitable for every TTL/NMOS output.

The shop's MC74HC245AN is a 20-pin through-hole part. Check its live stock and the listing before ordering; quantity changes as parts sell. For the wider context, begin with the 6502 parts guide.

Next: a one-way buffer

The 74HC245 is useful when data must travel in either direction. If a path only needs to carry eight signals one way, the SN74HCT541N guide shows a simpler alternative with two active-low output enables and TTL-compatible inputs. It cannot pass a read back in the opposite direction.