LF353N JFET op amp: understand feedback with a ×10 amplifier

An operational amplifier (op amp) is the building block behind amplifiers, filters, buffers and sensor interfaces. The LF353N contains two JFET-input op amps in an ordinary 8-pin DIP package, so it plugs straight into a breadboard. This guide explains what an op amp does, how two resistors set the gain, and follows one voltage step through the circuit from start to finish.

The basics: difference in, huge gain, feedback

An op amp has two inputs, a non-inverting (+) and an inverting (−), and one output. It amplifies the difference between the two inputs enormously: the LF353 has an open-loop gain of at least 25,000 (25 V/mV) and typically 100,000. Left on its own, even a few millivolts of difference would drive the output all the way towards a supply rail.

The trick is negative feedback: a resistor returns part of the output voltage to the inverting input. As soon as the output moves, it counteracts the difference that moved it. The output therefore settles by itself at the point where the two inputs are almost equal. That rule – with feedback, an op amp holds its two inputs at the same voltage – is the key to understanding almost every op-amp circuit.

The LF353's inputs are JFET transistors. They draw extremely little current (typically 50 pA input bias current), so high-impedance sources are barely loaded. The price is an input offset voltage of up to 10 mV at 25 °C, which is amplified along with the signal.

The LF353N pins

The LF353N is a dual op amp with the standard dual-op-amp pinout for an 8-pin DIP (the same as the LM1558). Both amplifiers share the supply pins:

  • Pin 1 – output A, pin 2 – inverting input A (−), pin 3 – non-inverting input A (+).
  • Pin 4 – V−: negative supply (e.g. −12 V), or GND with a single supply.
  • Pin 5 – non-inverting input B (+), pin 6 – inverting input B (−), pin 7 – output B.
  • Pin 8 – V+: positive supply (e.g. +12 V).
Top-view pinout of the LF353N in PDIP-8: left side pin 1 output A, pin 2 −IN A, pin 3 +IN A, pin 4 V−; right side pin 8 V+, pin 7 output B, pin 6 −IN B, pin 5 +IN B. The notch and dot mark pin 1.
LF353N top view (PDIP-8). Pins are counted anticlockwise from the notch; pin 1 is at the top left when the notch points up.

The circuit: an inverting amplifier with a gain of −10

We use op amp A as an inverting amplifier. The non-inverting input (pin 3) goes to GND. The signal enters through Rin = 10 kΩ to the inverting input (pin 2), and Rf = 100 kΩ feeds the output (pin 1) back to that same pin 2. The circuit runs from ±12 V: +12 V on pin 8, −12 V on pin 4 and a common GND. Each supply gets a 100 nF capacitor to GND close to the chip.

Schematic: Vin passes through Rin 10 kΩ to pin 2 of op amp A; Rf 100 kΩ connects pin 2 to the output pin 1, where Vout is taken. Pin 3 goes to GND. Pin 8 gets +12 V and pin 4 −12 V, each with 100 nF decoupling to GND. The unused op amp B is wired as a follower with pin 5 at GND and pin 6 tied to pin 7.
Inverting amplifier using op amp A. Op amp B is unused, so it is wired as a voltage follower with its input at GND instead of being left to float.

The gain is −Rf/Rin = −100 kΩ / 10 kΩ = −10. The minus sign means the output inverts the signal: +0.5 V in gives −5 V out. The circuit's input impedance is Rin = 10 kΩ, because pin 2 is held at 0 V. Bandwidth is about GBW / (1 + Rf/Rin) = 4 MHz / 11 ≈ 360 kHz (typical), and an input offset of up to 10 mV is multiplied by 11, so with no input the output may sit up to about 110 mV away from 0 V.

One cycle step by step

  1. At rest: Vin is 0 V. Pin 3 is at GND, so the output sits at almost 0 V, and so does pin 2. No current flows in Rin or Rf.
  2. The step arrives: Vin jumps to +0.5 V. For an instant, Rin pulls pin 2 slightly above pin 3 – the inverting input is now higher than the non-inverting one.
  3. The output responds: the amplified difference drives the output downwards. Its speed is limited by the slew rate, typically 13 V/µs (at least 8 V/µs), so the 5 V swing takes about 0.4 µs (at most about 0.6 µs).
  4. Feedback pulls back: as the output falls, Rf pulls pin 2 back down. The output stops when the current through Rin, 0.5 V / 10 kΩ = 50 µA, flows on through Rf: Vout = −50 µA × 100 kΩ = −5 V.
  5. Equilibrium: pin 2 is back at almost 0 V – a virtual ground. With at least 25 V/mV of open-loop gain, the remaining difference is below 0.2 mV at −5 V out. The output stays at −5 V for as long as the input is +0.5 V.
Three-row timing diagram: Vin steps from 0 V to +0.5 V; pin 2 shows a brief blip and returns to about 0 V; Vout falls linearly from 0 V to −5 V in about 0.4 µs and stays there.
Conceptual timing diagram for one +0.5 V step (not to scale). The output slope is the slew rate; pin 2 returns to virtual ground.

Build it on a breadboard

Build the amplifier with ±12 V from two bench supplies or a dual supply. Only switch the supplies on once the chip is the right way round. Check with a multimeter: 0 V in gives close to 0 V out, and +0.5 V from a voltage divider gives about −5 V.

  • 1 × LF353N (DIP-8), ideally in a socket.
  • Rin 10 kΩ and Rf 100 kΩ, 1 % metal film for an accurate gain.
  • 2 × 100 nF ceramic decoupling capacitors, one per supply, close to pins 8 and 4.
  • ±12 V supply with common GND; a potentiometer or voltage divider as the test source.
  • Output load: at least 2 kΩ.

More circuits: non-inverting amplifier and follower

Non-inverting amplifier: the signal goes straight to the + input, a resistor Rg runs from the − input to GND, and Rf still connects the output to the − input. The gain is 1 + Rf/Rg (e.g. 1 + 100 kΩ/10 kΩ = 11), the signal is not inverted, and the source sees the very high impedance of the JFET input.

Voltage follower (buffer): connect the output directly to the − input and feed the signal into the + input. The gain is 1, but a weak source can now drive a heavy load. It is also the safe way to park an unused op amp, as in the schematic above.

Single supply: the LF353 can run from e.g. 0/24 V, but then the signals must sit around a mid-supply reference made with a voltage divider, and neither the inputs nor the output get anywhere near 0 V. If you only have 5 V, the LF353 is the wrong choice – it needs at least ±6 V (12 V in total) to work normally.

Limits and pitfalls

  • Supply: absolute maximum ±18 V; the datasheet describes normal operation down to ±6 V. Specifications are given at ±15 V.
  • Not rail-to-rail: at ±15 V into 10 kΩ the output is guaranteed to reach ±12 V (typically ±13.5 V). Allow up to 3 V of headroom to each rail. The input common-mode range is guaranteed to ±11 V at ±15 V.
  • Inputs below V−: no input may go below the negative supply – that can cause large currents and destroy the chip. If an input goes below the negative common-mode limit, the output may jump high (phase reversal).
  • Never reverse the supply: reversed polarity, or a chip inserted backwards in its socket, can burn it out.
  • Load: at least 2 kΩ for full output swing; the output survives a short circuit, but offset increases under heavy load.
  • ESD and temperature: limited ESD protection (1000 V HBM) – store in conductive foam. Operating temperature 0 to 70 °C.
  • Offset: up to 10 mV at 25 °C. For DC precision at high gain, choose a precision op amp or add trimming.

Related guides

A 555 timer contains comparators – a kind of op amp without feedback; see the LMC555 CMOS timer guide. To show an amplified audio signal on an LED bar, the LM3916N level meter guide explains how a ten-step LED driver reads a voltage.

Source and stocked part

The stocked part is National Semiconductor LF353N: the LF353 in an 8-pin plastic DIP (National "N" package, equivalent to TI's PDIP package "P"), 0 to 70 °C, new old stock (NOS). Pinout, supply, input and output limits, slew rate, GBW and application notes were checked against TI datasheet LF353-N, SNOSBH3F (revised March 2013).

View the LF353N product · Read the TI datasheet