MC14093B Schmitt trigger: debounce a button, build a blinker

A push button does not switch cleanly, and a slowly charging capacitor passes through the forbidden zone between LOW and HIGH. The MC14093B solves both problems with four NAND gates whose inputs have hysteresis. This guide explains the idea and builds one complete circuit: a debounced button that starts an LED blinker.

First the basics: a NAND gate

A NAND gate has two inputs and one output. The output is LOW only when both inputs are HIGH; in every other case it is HIGH. If you tie both inputs together, the gate becomes an inverter: HIGH in gives LOW out and vice versa. If you hold one input HIGH, the other input passes through inverted; hold it LOW and the output is stuck HIGH. That last property turns a NAND input into an enable switch, which we use below. If gates are new to you, the MC74HC08AN AND-gate guide starts with switches and an LED.

What a Schmitt trigger adds

An ordinary CMOS input has one switching point somewhere around half the supply voltage. If the input voltage creeps slowly through that point, or carries a little noise, the output can flip back and forth several times. A Schmitt-trigger input has two thresholds instead:

  • VT+ – a rising input must climb above this level before the gate sees HIGH.
  • VT− – a falling input must drop below this lower level before the gate sees LOW again.

The gap between them is the hysteresis (VH). Small wiggles inside the gap are ignored, so a slow or noisy edge produces exactly one clean output step.

Graph of a slow, noisy input crossing a dashed upper threshold VT+ and lower threshold VT−, with the inverted output switching only once per crossing.
With the inputs tied together the gate inverts: the output falls once the input passes VT+ and rises only after the input drops below VT−.

The Motorola CMOS data book gives these values for the MC14093B at VDD = 5 V and 25 °C: VT+ 1.80–4.05 V (typically 2.70 V), VT− 1.63–3.66 V (typically 2.44 V), and hysteresis 0.17–0.6 V (typically 0.26 V). Notice how wide the ranges are: the thresholds vary from chip to chip, so design for the minimum and maximum, not the typical value.

The chip and its pins

The MC14093B belongs to the 4000-series CMOS family (like the MC14002 NOR gate). It runs from 3 to 18 V and is pin-compatible with the CD4093 and the ordinary MC14011B NAND gate. The stocked MC14093BCP is the C-series part (−40 to +85 °C) in the 14-pin plastic DIP (P suffix, Motorola case 646), so it fits directly into a breadboard.

MC14093BCP DIP-14 top view: pins 1, 2 inputs of gate A and pin 3 its output; pin 4 output B, pins 5, 6 inputs B; pin 7 VSS; pins 8, 9 inputs C; pin 10 output C; pin 11 output D; pins 12, 13 inputs D; pin 14 VDD.
Top view with the notch at the top. Note that pins 3 and 4 are both outputs, and pins 10 and 11 likewise.

Three rules for every CMOS gate: connect pin 14 (VDD) to +5 V and pin 7 (VSS) to 0 V with a 100 nF capacitor right at the chip; tie every unused input to VDD or VSS, because a floating CMOS input can drift into the threshold zone; and leave unused outputs open.

The complete circuit

Schematic: 100 kΩ from VDD to node X, 100 nF from X to VSS, button with 10 kΩ from X to VSS. Gate A (pins 1, 2 tied, output pin 3) feeds pin 5 of gate B; gate B output pin 4 feeds back to pin 6 through 1 MΩ with 1 µF from pin 6 to VSS. Gate C (pins 8, 9 tied) buffers pin 4; output pin 10 drives an LED through 2.2 kΩ.
Gate A debounces the button, gate B is an oscillator that only runs while pin 5 is HIGH, and gate C buffers the LED so the load does not disturb the timing.

Build it on a breadboard at 5 V:

  1. Place the MC14093BCP across the breadboard gap. Pin 14 to +5 V, pin 7 to 0 V, 100 nF between them.
  2. Debounce network: 100 kΩ from +5 V to a node we call X; 100 nF from X to 0 V; the push button in series with 10 kΩ from X to 0 V.
  3. Gate A as inverter: connect pins 1 and 2 together to X. Pin 3 is the clean “button pressed” signal.
  4. Gate B as gated oscillator: pin 3 to pin 5. 1 MΩ from pin 4 to pin 6, and 1 µF from pin 6 to 0 V (with an electrolytic, minus to 0 V).
  5. Gate C as buffer: pins 8 and 9 together to pin 4. From pin 10 run 2.2 kΩ to the LED anode, LED cathode to 0 V.
  6. Gate D unused: pins 12 and 13 to 0 V, pin 11 open.

One complete press, step by step

  1. Idle. 100 kΩ pulls X to 5 V. Both inputs of gate A are HIGH, so pin 3 is LOW. A LOW on pin 5 forces gate B’s output (pin 4) HIGH, whatever pin 6 is doing; the capacitor charges to 5 V and the oscillator rests. Gate C inverts the HIGH, so pin 10 is LOW and the LED is off.
  2. Press. The button connects X to 0 V through 10 kΩ. The 100 nF capacitor discharges with a time constant of about 0.9 ms and settles at 5 V × 10 k / 110 k ≈ 0.45 V – safely below the lowest possible VT− (1.63 V). As X passes VT−, pin 3 goes HIGH exactly once.
  3. Bounce. The contacts chatter for a few milliseconds. Each brief opening lets the capacitor recharge through 100 kΩ only a little (time constant 10 ms), far from VT+, so pin 3 stays HIGH. Without the Schmitt input and the capacitor, a counter such as the one in the MC14027B J-K flip-flop guide would count every bounce.
  4. Blink. Pin 5 is now HIGH, so gate B inverts pin 6. Pin 4 is HIGH, the 1 µF capacitor charges through 1 MΩ; when it passes VT+, pin 4 drops LOW and the capacitor discharges; when it falls below VT−, pin 4 goes HIGH again. The capacitor voltage swings between the two thresholds and pin 4 is a square wave. Gate C inverts it and the LED blinks.
  5. Release. X charges back up through 100 kΩ. After roughly 4–17 ms (0.45–1.7 time constants, depending on where this chip’s VT+ lies) it crosses VT+, pin 3 goes LOW, gate B stops with pin 4 HIGH, and the LED goes out.

How fast does it blink?

The capacitor travels only between VT− and VT+, so the period depends on the thresholds: T ≈ R·C·[ln((VDD−VT−)/(VDD−VT+)) + ln(VT+/VT−)]. With the typical 5 V values that is about 0.21 × R·C, so 1 MΩ and 1 µF give roughly 0.2 s per cycle, or about 5 Hz. Because the hysteresis may lie anywhere between 0.17 and 0.6 V, another chip might blink at roughly 2 Hz or 7 Hz. Treat the formula as an estimate and change R or C to tune; for an accurate frequency use a crystal or a dedicated timer.

Limits to keep in mind

  • Weak outputs. At 5 V the CP version is only guaranteed to source 0.44 mA at 4.6 V or 2.1 mA at 2.5 V. With 2.2 kΩ the LED gets roughly 1 mA, so choose a high-efficiency LED. For more current, drive an NPN transistor from pin 10.
  • Speed. Typical propagation delay is 125 ns at 5 V (250 ns maximum). Ideal for buttons, sensors and oscillators up to the kHz range, not for fast bus logic.
  • Input voltage. Keep every input between VSS and VDD. Signals from another supply need a level shift.
  • Contacts. The 10 kΩ resistor limits the current when the button discharges the capacitor, which protects the contacts.

The stocked part and sources

The stocked part is the Motorola MC14093BCP: four 2-input NAND Schmitt triggers in a 14-pin plastic DIP. Pinout, package, thresholds and timing in this guide come from the MC14093B pages of Motorola’s 1988 CMOS Logic Data book; onsemi’s current datasheet covers the same device.

View the MC14093BCP product page · MC14093B datasheet (onsemi) · Motorola CMOS Logic Data (1988)