Retro computing field guide · Part 2

How a 74HC138 selects a memory chip

The CPU gives every byte an address. The 74HC138 turns part of that address into a signal saying which chip is allowed to answer. Let’s build that idea one step at a time.

New to the buses? Start with part 1

Why select anything?

RAM, ROM and I/O chips share the CPU’s eight data wires. During a read, one chip must put a value on those wires while the others remain silent. Each chip therefore has a chip-enable or chip-select input, often written /CE or /CS. “Selecting a device” means activating that input for the address range assigned to it. This is separate from selecting an individual byte within that chip.

The CPU has address wires A0 through A15. Lower wires can choose a byte inside a memory chip. Higher wires can choose which chip is enabled. A 74HC138 reads three binary inputs, A, B and C, and activates one of eight outputs. The slash on an output name means that low selects it.

Find the pins first

Top-view 74HC138 pinout: left pins 1 A, 2 B, 3 C, 4 G2A, 5 G2B, 6 G1, 7 Y7, 8 ground; right pins 16 VCC, 15 Y0, 14 Y1, 13 Y2, 12 Y3, 11 Y4, 10 Y5, 9 Y6
Top view, with the notch at the pin-1 end. Pin numbers and functions follow the manufacturer’s 16-pin package diagram. A slash (/) marks an active-low signal.

For a straightforward always-enabled example, connect pin 6 (G1) high and pins 4 and 5 (/G2A, /G2B) low. The chip needs power on pin 16 and ground on pin 8. Put a 0.1 µF bypass capacitor close to those supply pins. These are conceptual connections, not a complete board schematic: check logic-level compatibility and timing before building.

Turn addresses into eight windows

Connect CPU A13 to decoder input A (pin 1), A14 to B (pin 2), and A15 to C (pin 3). Why those lines? The lower 13 bits, A0–A12, can count from 0 to 8191: 8 KB of positions inside one window. The next three bits identify which of the eight windows the CPU is visiting.

Y0 · $0000–$1FFF

A15 A14 A13 = 000. Output pin 15 goes low.

Y1 · $2000–$3FFF

001. Output pin 14 goes low.

Y2 · $4000–$5FFF

010. Output pin 13 goes low.

Y3 · $6000–$7FFF

011. Output pin 12 goes low.

Y4 · $8000–$9FFF

100. Output pin 11 goes low.

Y5 · $A000–$BFFF

101. Output pin 10 goes low.

Y6 · $C000–$DFFF

110. Output pin 9 goes low.

Y7 · $E000–$FFFF

111. Output pin 7 goes low. This region includes the reset vector.

Eight 8 KB address ranges selected by outputs Y0 through Y7; E000 through FFFF is Y7
With A15–A13 as inputs, each active-low output covers one 8 KB window. The highlighted range contains $E123.

Walk through address $E123

  1. The CPU places $E123 on A0–A15. Its top bits A15 A14 A13 are 111.
  2. The enabled 74HC138 pulls /Y7 low (pin 7). All other Y outputs stay high.
  3. If an 8 KB ROM has its /CE connected to Y7, that ROM is selected. Its own A0–A12 inputs see $0123, the offset within the ROM.
  4. For a read, the ROM can place the byte at that offset on D0–D7. RAM and I/O must remain inactive.
Important limits. A 32 KB memory chip is larger than one 8 KB window; one Y output will expose only one quarter of it. A VIA has far fewer than 8 KB of registers, so its registers will repeat (“mirror”) through a whole window unless you decode more address bits. Also gate read/write control correctly and verify propagation delay so two devices never drive the data bus together.

Next, see how an 74HC245 controls the direction of an eight-bit data bus after an address has selected the device.

The shop lists an MC74HC138AD in SOIC-16 surface-mount packaging. It will not plug directly into a solderless breadboard; use an adapter or find a through-hole part if that is what your build needs.

Browse Retro ICs