Build a complete 80C31 computer on breadboards

The Philips P80C31SFPN is a ROM-less 8051-family CPU. It cannot run from power alone: it needs a clock, a reset circuit, an external program ROM, and a latch to separate the low address byte from the data bus. This build adds 8 KB of external RAM and two diagnostic LEDs. Every active part named below is sold by iMania; the remaining materials are ordinary passives, hookup wire, a regulated 5 V supply, and the tools needed to program the ROM. This is a wiring guide, not a claim that the assembled circuit has been bench-tested.

Parts

• 1 × Philips P80C31SFPN, DIP-40 — 80C31 CPU — ROM-less processor.
• 1 × SN74ALS873BNT, DIP-24 — 8-bit latch — Holds address A0–A7.
• 1 × AT27C512R-55PC, DIP-28 — 64 KB OTP ROM — Program memory; program it before assembly.
• 1 × HM6264LP-15, DIP-28 — 8 KB SRAM — External data memory.
• 1 × 11.0592 MHz HC49/SMT crystal — NKG crystal — CPU clock; solder two short leads for breadboard use.
• 2 × solderless 630-point breadboards — MCBB630 — Spread out the buses.
• 2 × through-hole white LEDs — Vishay TLWW76 — Pass/fail indicators.

Also use a regulated 5 V supply, hookup wire, a 100 nF ceramic capacitor directly across each IC's supply pins, one 10 µF rail capacitor, two 22 pF ceramic capacitors for the crystal, one 10 µF reset capacitor, one 10 kΩ resistor, two 1 kΩ LED resistors, and an optional normally-open reset button. A 40-pin socket is optional; the shop has a DIP-40 socket. The SMT crystal needs two short soldered wires; do not jam its surface-mount pads into breadboard contacts. A ROM programmer is a preparation tool, not part of the running circuit. An unprogrammed OTP ROM will not boot.

What happens on one memory cycle

The CPU first puts A0–A7 on port 0 and A8–A15 on port 2. ALE goes high, making the SN74ALS873BNT transparent; when ALE falls, the latch holds A0–A7. Port 0 can then become the D0–D7 data bus. A low PSEN lets the ROM drive the bus for an instruction fetch. A low RD lets the RAM drive it for a MOVX read; a low WR writes RAM. The ROM and RAM have separate address spaces even though they share the same data wires. Never join their output-enable pins: that would make both chips drive the bus together.

Wiring, in order

1. Power and reset. With power disconnected, put the four ICs across the breadboard center gaps, notch at the same end. Join all ground rails and all +5 V rails, checking split rails for continuity. CPU pin 40, latch pin 24, ROM pin 28, and RAM pin 28 go to +5 V. CPU pin 20, latch pin 12, ROM pin 14, and RAM pin 14 go to ground. Put 100 nF close to each IC, plus 10 µF across the rails. Tie CPU EA pin 31 firmly to ground, because this ROM-less device must fetch externally. CPU RST pin 9 gets 10 kΩ to ground and 10 µF to +5 V (electrolytic positive lead at +5 V); the optional button connects RST to +5 V. Reset is active high. Hold it high long enough for the oscillator to start.
2. Clock. Connect the 11.0592 MHz crystal between CPU XTAL1 pin 19 and XTAL2 pin 18. Put one 22 pF capacitor from each crystal pin to ground. Keep this loop very short and away from the long data bus. This SMT part needs soldered leads; if its mechanical mounting is unreliable, do not power the board until it is secure. This CPU variant is rated to 16 MHz, so 11.0592 MHz is inside its speed range.
3. Multiplexed data/address bus. For each bit n=0…7, connect CPU P0.n to latch Dn, ROM On, and RAM I/On. CPU P0.0…P0.7 are pins 39, 38, 37, 36, 35, 34, 33, 32. ROM and RAM D0…D7 are pins 11, 12, 13, 15, 16, 17, 18, 19. Latch D0…D7 are pins 3, 4, 5, 6, 7, 8, 9, 10. During external-memory cycles port 0 has internal pull-ups; no separate P0 resistor pack is required for this bus.
4. Low address latch. Latch Q0…Q7 are pins 22, 21, 20, 19, 18, 17, 16, 15. Connect each to matching ROM and RAM A0…A7. On both memories, A0…A7 are pins 10, 9, 8, 7, 6, 5, 4, 3. Connect CPU ALE pin 30 to latch LE pins 23 and 14. Hold latch active-low OE pins 2 and 11 at ground and active-low CLR pins 1 and 13 at +5 V. Both four-bit halves must be enabled.
5. High address. CPU P2.0…P2.7, pins 21…28, go to ROM A8…A15. ROM A8…A15 pins are 25, 24, 21, 23, 2, 26, 27, 1 respectively. RAM only has A8…A12: connect P2.0…P2.4 to RAM pins 25, 24, 21, 23, 2. P2.5…P2.7 do not go to RAM.
6. Control. ROM CE pin 20 goes to ground; ROM OE/VPP pin 22 goes only to CPU PSEN pin 29. RAM active-low CS1 pin 20 goes to ground; RAM active-high CS2 pin 26 goes to +5 V. RAM OE pin 22 goes only to CPU RD/P3.7 pin 17; RAM WE pin 27 goes only to CPU WR/P3.6 pin 16. With no address decoder, the 8 KB RAM appears repeatedly throughout the 64 KB external-data space. That is intentional for this minimal build; software should use 0000h–1FFFh for RAM.
7. Indicators. For each LED connect +5 V → 1 kΩ → LED anode, then LED cathode to CPU P1.0 pin 1 or P1.1 pin 2. A low output lights an LED. Do not connect LEDs without series resistors.

Program and first boot

The supplied test program source and 64 KB ROM binary start at code address 0000h. The program writes 5Ah to external RAM address 0000h and reads it back. If it matches, P1.0 blinks; if it fails, P1.1 stays lit. Program the 64 KB binary into a blank AT27C512R-55PC with a programmer that explicitly supports that exact device, and verify the programmed ROM byte-for-byte. It is one-time programmable: a wrong image needs another blank chip. Disconnect power before inserting or removing any IC.

Power the breadboards from a current-limited regulated 5 V source. Check for 5 V and ground at each chip before inserting the ROM. On boot, P1.0 should blink and P1.1 should remain off. If neither responds, check reset release, oscillator activity, EA low, ALE pulses, ROM PSEN/OE, and the first three code bytes at address 0000h. If P1.1 lights, re-check the RAM's two chip selects, RD/WR, and the shared data/address mapping. Do not probe the crystal with a heavy scope lead: its loading can stop oscillation. This design has not been physically bench-verified; long breadboard wires can make an otherwise correct 11 MHz circuit unreliable.

Source documents

Pin numbers and timing were checked against the Philips 80C31/80C32 datasheet, TI SN74ALS873B datasheet, Microchip AT27C512R datasheet, and the original Hitachi HM6264LP-15 datasheet (1985 Hitachi IC Memories Data Book, page 158). Check the markings and notches on your actual parts before applying power.