MC14027BCP guide: the J-K flip-flop that counts

What a flip-flop remembers that a gate cannot

A gate has no past. Put the same levels on a NOR gate today and tomorrow and you get the same answer, which is why a MC14002B four-input NOR can decide something but never remember it. A flip-flop stores one bit and changes it only when told to. On this part the moment it is told is the rising edge of the Clock input — the data sheet is explicit that the state is retained indefinitely while the clock sits high or low, and information transfers to the output only on the positive-going edge. Each of the two flip-flops gives you both the stored bit Q and its exact opposite Q-bar on a separate pin, which costs nothing and often saves an inverter.

J and K: choosing what the clock will do

What makes it a J-K rather than a D is that J and K do not set the output directly; they choose what the next clock edge will do. There are four combinations and they are worth learning as a set. With J=1 and K=0 the next rising edge makes Q become 1, no matter what it was. With J=0 and K=1 the next edge makes Q become 0. With J=0 and K=0 the edge changes nothing, so the chip ignores the clock and holds. And with J=1 and K=1 the edge toggles: Q becomes the opposite of what it was. A D-type register such as the MC74HC173N can only copy what you hand it, so making it toggle means feeding its own inverted output back round the outside. The J-K does it internally, which is why it is the usual starting point for a counter.

Set and Reset, and the one combination to avoid

Set and Reset work outside the clock entirely. Both are active high and asynchronous: a high level on Reset drives Q to 0 immediately, with no clock edge needed, and a high level on Set drives Q to 1 the same way. While either one is held high it overrides J, K and the clock completely, so a power-on reset pulse on R is the normal way to make a counter start from a known zero. There is one combination to avoid: with Set and Reset both high the data sheet shows Q and Q-bar both going to 1, which breaks the promise that the two pins are opposites, and the state the chip lands in when you release them is not defined. Keep the unused one low. At 5 V a Set or Reset pulse must be at least 250 ns wide to be guaranteed to take effect.

One complete divide-by-two

Here is the complete transaction that turns this chip into a divider. Power it with VDD on pin 16 and VSS on pin 8; the data sheet allows anything from 3.0 to 18 V, and 5 V is the usual choice next to 74HC parts. Take the first flip-flop and tie JA (pin 6) and KA (pin 5) both high to VDD — that is the toggle instruction, and you leave it wired that way permanently. Tie SA (pin 7) and RA (pin 4) low to VSS so neither override is active. Now feed your clock into CA (pin 3) and watch QA (pin 1). On the first rising edge QA goes high. It stays high through the whole rest of that clock period and through the falling edge, because only the positive-going edge matters. On the second rising edge QA goes low again. Two input edges have produced one complete output cycle, so QA is your clock divided by two, and it comes out as a clean square wave regardless of how lopsided the input was. At 5 V the data sheet guarantees this up to 1.5 MHz, with 3.0 MHz typical, and the clock must be high for at least 330 ns and low for at least 330 ns. If you drive J and K from logic rather than tying them high, they must be stable 140 ns before the edge and held 140 ns after it. Expect up to 350 ns from the clock edge to a settled output at 5 V.

Chaining stages into a counter

Chaining stages is what makes it count rather than merely divide. Each stage halves the frequency again, so after two stages you have a quarter, after three an eighth. The detail that catches people out is which output you chain from. Because this part triggers on the rising edge, feeding QA into the next stage CB gives you a binary down-counter — the next stage only sees a rising edge when the previous Q goes from 0 to 1, which happens on the odd counts. Feed Q-bar A (pin 2) into CB (pin 13) instead and the same two flip-flops count up in binary, with QA as the low bit and QB as the high bit: 00, 01, 10, 11 and back to 00. That is a full two-bit counter in one package, and tying both Reset pins together gives you a single wire that clears it. Four bits means two of these chips and gives you the sixteen states a BCD-to-7-segment decoder like the MC74HC4511N expects at its input, though a BCD display needs the count stopped at nine rather than running to fifteen. Note that this is a ripple counter: each stage waits for the one before it, so the delays add up along the chain and the outputs are briefly wrong after every edge. That is fine for dividing a clock or blinking an LED, and it is the reason real address logic uses a clocked decoder such as the 74HC138 on settled outputs rather than decoding a ripple chain directly.

The MC14027BCP pinout

The figure shows the stocked CP-suffix 16-pin plastic DIP from above, with pin 1 at the notch and numbering running counter-clockwise. The two flip-flops are laid out as near mirror images. Flip-flop A occupies pins 1 to 7: pin 1 is QA, pin 2 is Q-bar A, pin 3 is the clock CA, pin 4 is Reset A, pin 5 is KA, pin 6 is JA and pin 7 is Set A. Pin 8 is VSS, the negative supply. Flip-flop B runs back up the other side: pin 9 is Set B, pin 10 is JB, pin 11 is KB, pin 12 is Reset B, pin 13 is the clock CB, pin 14 is Q-bar B and pin 15 is QB. Pin 16 is VDD. Tie every unused input to VSS or VDD and never leave one floating — the data sheet states this as a requirement, not a suggestion, because a floating CMOS input drifts to the threshold and makes the chip draw current and switch at random. If you only need one of the two flip-flops, its unused twin still needs its J, K, C, S and R pins tied somewhere. Unused outputs, by contrast, should be left open.

Where 4000B differs from 74HC and TTL

This is 4000B-series CMOS, not 74HC, and the difference shows up as soon as you connect it to something else. The upside is the supply range: 3.0 to 18 V, so the same chip runs on a 9 V battery or a 12 V rail where a 74HC part would not. Noise immunity is typically 45% of the supply, and quiescent current is about 2.0 nA per package at 5 V, which is effectively nothing. The catch is drive and speed. The data sheet rates the outputs for two low-power TTL loads or a single low-power Schottky TTL load, so this is not a part for driving a bus or several inputs across a board — put a 74HCT541 buffer after it if you need to. Going the other way, at a 5 V supply the chip needs at least 3.5 V to read an input as high, and an LSTTL output only guarantees 2.7 V, so driving these inputs from older TTL needs a pull-up resistor; 74HC outputs swing close to the rail and connect directly. Finally, it is a pin-for-pin replacement for the CD4027B, so anything written for that part applies here, and the CP suffix means the limited temperature grade, −40 to +85 °C.

The chip described here is in stock as a Motorola MC14027BCP in the 16-pin plastic DIP. See the MC14027BCP product.

Sources: onsemi MC14027B Dual J-K Flip-Flop data sheet (MC14027B/D, Rev 9, August 2025) for the pin assignment, truth table and timing, and the 1978 Motorola CMOS Data Book, page 7-80, for the CP suffix (plastic package, Case 648) and the −40 to +85 °C grade. onsemi PDF · Motorola 1978 PDF.