SN74LS259B addressable latch: eight outputs from five lines

You want to switch eight LEDs, relays or enable lines, but your controller has only a handful of pins left. The SN74LS259B stores eight separate bits and lets you change any single one of them with five control lines, while the other seven stay exactly as they were. This guide explains the idea, walks through one complete write, and builds a test circuit with switches and LEDs.

First the basics: what a latch is

A latch is a one-bit memory cell. While its enable signal is active, the output simply follows the data input. When enable is released, the output freezes at the last value and keeps it until the next write. The SN74LS259B contains eight such latches, Q0 to Q7, which all share one data input D.

So how do you choose which latch to write? With an address. The three select inputs S0, S1 and S2 form a 3-bit binary number from 0 to 7, and only the latch with that number listens to D. This is the same address-decoding principle that the 74HC138 address-decoding guide and the MC14515B decoder guide describe; here a memory cell sits behind every decoder output.

The control signals

  • S0, S1, S2 (pins 1–3) – the address. S0 is the least significant bit, so S2 S1 S0 = H L H selects latch 5.
  • D (pin 13) – the bit to store.
  • G (pin 14) – enable, active LOW (the bar over the name means “active when LOW”). While G is LOW, the addressed latch follows D. When G goes HIGH, the value is stored.
  • CLR (pin 15) – clear, also active LOW. Keep it HIGH for normal operation.

The combination of CLR and G gives four modes, taken from the function table in TI’s datasheet:

  • CLR HIGH, G LOW: addressable latch – the addressed output follows D, the other seven hold.
  • CLR HIGH, G HIGH: memory – all eight outputs hold, whatever happens on D and S0–S2.
  • CLR LOW, G LOW: 1-of-8 demultiplexer – the addressed output follows D, all others are LOW.
  • CLR LOW, G HIGH: clear – all eight outputs LOW.
SN74LS259BN DIP-16 top view: pins 1 to 3 S0, S1, S2; pins 4 to 7 Q0 to Q3; pin 8 GND; pins 9 to 12 Q4 to Q7; pin 13 D; pin 14 G-bar; pin 15 CLR-bar; pin 16 VCC.
Top view with the notch at the top. Note that the outputs are split: Q0–Q3 on pins 4–7 and Q4–Q7 on pins 9–12, with GND on pin 8 in between.

One complete write cycle

Say we want to set output Q5 to 1 without disturbing Q0–Q4, Q6 or Q7. Start with CLR HIGH and G HIGH (memory mode):

  1. Set the address. Put S2 S1 S0 = H L H (binary 101 = 5). Because G is HIGH, nothing changes yet.
  2. Set the data. Put D HIGH.
  3. Open the latch. Pull G LOW. Q5 now follows D and goes HIGH after typically 15 ns (24 ns maximum). The other outputs do not move.
  4. Close the latch. Return G HIGH. Q5 is now stored as 1.
  5. Move on. Only now may the address and D change for the next write.
Timing diagram: the address S2 S1 S0 changes to H L H and D rises; G-bar goes LOW for at least 17 ns and then HIGH; Q5 rises while G-bar is LOW and remains HIGH afterwards; the other outputs hold their old value. The address must be stable at least 17 ns and D at least 20 ns before G-bar rises.
One write: address and data are set up first, G-bar opens and closes the addressed latch, and only then may the address change.

The datasheet gives the timing limits for the SN74LS259B: G must be LOW for at least 17 ns, the address must be stable at least 17 ns and D at least 20 ns before G rises, and the hold time after G rises is 0 ns. TI also advises that G be held HIGH while the address lines are changing; otherwise the latches you pass through on the way to the new address can briefly catch the data. With hand switches or a microcontroller these limits are easy to meet; they matter when you drive the chip from fast logic.

Build a test circuit

Schematic: switches pull S0, S1, S2 and D to GND, push buttons pull G-bar (WRITE) and CLR-bar (RESET) to GND; each of these six inputs has a 10 kΩ pull-up to +5 V. Outputs Q0 to Q7 on pins 4, 5, 6, 7, 9, 10, 11 and 12 each connect to an LED cathode; each LED anode goes through 1 kΩ to +5 V.
Four switches set address and data, WRITE strobes G-bar and RESET clears all latches. An LED lights when its output is LOW.
  1. Place the SN74LS259BN across the breadboard gap. Pin 16 to +5 V, pin 8 to GND, and a 100 nF capacitor between them right at the chip. LS-TTL needs 4.75–5.25 V.
  2. Give S0 (pin 1), S1 (pin 2), S2 (pin 3), D (pin 13), G (pin 14) and CLR (pin 15) each a 10 kΩ pull-up to +5 V. An open switch then reads HIGH and a closed switch LOW.
  3. Connect a switch from each of S0, S1, S2 and D to GND, and a push button from G (WRITE) and from CLR (RESET) to GND.
  4. For each output, run an LED from +5 V through 1 kΩ to the output pin: anode towards the resistor, cathode to Q0 (pin 4), Q1 (5), Q2 (6), Q3 (7), Q4 (9), Q5 (10), Q6 (11) and Q7 (12).

Why do the LEDs hang from +5 V? An LS-TTL output can sink 8 mA when LOW but is only specified to source 0.4 mA when HIGH. Wired this way, a red LED gets about 2.5–3 mA, which is well inside the limit, but the logic is reversed: an LED is lit when its bit is 0.

Try it

  1. Press RESET. The chip clears and all eight outputs go LOW, so all eight LEDs light. (After power-up the latches start in an unknown state, so always clear first.)
  2. Set S2 open, S1 closed, S0 open (H L H = 5) and leave D open (HIGH).
  3. Press and release WRITE. The LED on Q5 goes out; the other seven stay lit.
  4. Close D and press WRITE again: the LED on Q5 lights once more. Choose another address and repeat – each write changes only one LED.

Contact bounce on WRITE is harmless here: each bounce simply writes the same D value to the same latch again. Do not change the switches while WRITE is held down, though, because the chip then behaves as a live demultiplexer.

Driving it from a microcontroller

Connect five 5 V GPIO pins to S0, S1, S2, D and G and keep CLR HIGH (or use a sixth pin for it). A write then is: set G HIGH, write the three address bits, write D, set G LOW, set G HIGH. A 3.3 V controller can usually drive the inputs, because an LS-TTL input recognises anything above 2 V as HIGH and below 0.8 V as LOW, but check that its pins can sink the 0.4 mA each LOW input draws. Do not feed the chip’s 5 V outputs back into a 3.3 V pin. If you need to read eight switches rather than drive eight loads, the MM74HC165 shift-register guide covers the opposite direction; for writing all eight bits at once, see the MC74HC173 register guide.

Limits to keep in mind

  • Supply. 4.75–5.25 V; the chip draws typically 22 mA and up to 36 mA.
  • Outputs. Up to 8 mA sink at a LOW level of 0.5 V maximum; only 0.4 mA source. Use a transistor or driver for relays and larger loads.
  • Inputs. HIGH ≥ 2 V, LOW ≤ 0.8 V. Tie unused inputs firmly to a level instead of leaving them open.
  • Temperature. The SN74LS259B is specified from 0 to 70 °C.

The stocked part and sources

The stocked part is the Texas Instruments SN74LS259BN: an 8-bit addressable latch in Low-Power Schottky TTL in a 16-pin plastic DIP (TI package N), so it fits straight into a breadboard. Pinout, function table, timing and electrical limits in this guide come from TI datasheet SDLS086, whose package addendum lists SN74LS259BN as PDIP (N), 16 pins.

View the SN74LS259BN product page · SN74LS259B datasheet (Texas Instruments)