RETRO ICs / LOGIC LEVELS

SN74AHCT08PWR: an AND gate that lifts 3.3 V to 5 V logic

A 3.3 V microcontroller output looks like a high to a human reading a meter. To a 5 V CMOS input it can look like nothing at all. This guide explains why, and how one quad AND gate solves it.

Why 3.3 V is not automatically a “high”

A plain CMOS input decides between high and low by comparing the input to a fraction of its own supply. For 74HC logic the data sheet guarantees a high only from 3.15 V when the chip runs on 4.5 V – roughly 0.7 × VCC. Run the same chip on 5 V and it wants about 3.5 V before a high is guaranteed.

A 3.3 V output cannot reach that. It often appears to work on the bench at room temperature, and then fails on a cold morning, on a different batch, or when the supply drifts up. “It worked once” is not the same as “the data sheet guarantees it”.

Old TTL logic used fixed thresholds instead: anything at or above 2 V is a high, anything at or below 0.8 V is a low, regardless of supply. 3.3 V clears a 2 V threshold with 1.3 V to spare.

A 3.3 V microcontroller GPIO feeds input 1A of an AND gate whose second input 1B is tied high; the 1Y output drives a 5 V CMOS input. Below, a voltage scale shows a 3.3 V signal clearing the AHCT 2.0 V threshold but not the 3.5 V threshold of a 74HC input at 5 V.
Signal principle, not a finished schematic. The gate is powered from 5 V; only its input thresholds are TTL-like.

What the “HCT” in AHCT actually buys you

The SN74AHCT08 is CMOS inside – fast, almost no static current – but its inputs are deliberately given TTL thresholds: VIH 2 V minimum, VIL 0.8 V maximum over the whole 4.5 V to 5.5 V supply range. The outputs are ordinary CMOS outputs that swing to the 5 V rail.

That combination is the level shift. Feed 3.3 V logic into the input, take 5 V logic out. TI states it plainly in the data sheet: the TTL inputs accept voltages down to 3.3 V and translate up to 5 V.

This works in one direction only. The outputs swing all the way to VCC, so you must not point them at a 3.3 V input that is not 5 V tolerant. For 5 V → 3.3 V you need a different arrangement, such as the open-drain SN74LVC07A with a pull-up to the lower rail.

The inputs themselves are rated to 5.5 V at any valid supply, so a 5 V source driving an AHCT input is fine.

One complete transaction, step by step

Use gate 1. VCC is pin 14, GND is pin 7, and the 3.3 V board and the 5 V board must share that ground. Put a 100 nF capacitor between pin 14 and pin 7, close to the chip.

  1. Open the gate. An AND gate gives Y = A · B. Tie 1B (pin 2) to 5 V and the gate simply passes 1A through to 1Y. The second input is not wasted – see below.
  2. Drive the input. Connect the 3.3 V GPIO to 1A (pin 1). A 3.3 V high sits 1.3 V above the 2 V threshold; a 0 V low sits 0.8 V below the 0.8 V threshold. Keep the edges faster than 20 ns per volt, which the data sheet requires.
  3. Read the output. 1Y (pin 3) now switches between ground and the 5 V rail. Lightly loaded (50 µA) it reaches at least 4.4 V; even pulling a full 8 mA it still guarantees 3.8 V, which clears the 3.5 V that a 5 V 74HC input wants.
  4. Count the delay. From A or B to Y, typically 5 ns and at most 8 ns with a 15 pF load, rising to 9 ns at 50 pF, at 5 V and 25 °C.

The chip has four identical gates, so one package translates four signals – for example a 3.3 V SPI master’s clock, chip-select and data lines into a 5 V peripheral.

Using the second input as a real enable

Instead of tying 1B permanently high, drive it from a control line. The gate then becomes a switch: while 1B is high the signal passes, while 1B is low the output is held low. That is the clean way to start and stop a clock without generating a runt pulse on a chip-select line.

If the enable has to come from an address or a device number, a decoder produces exactly one active line at a time – see the 74HC138 address-decoding guide. Note that a ’138 output is active low, so it must be inverted before it can enable an AND gate.

The numbers that matter

SN74AHCT08 (commercial range)Value
Supply voltage4.5–5.5 V, −40 to 125 °C
Input thresholdsHigh ≥ 2 V, low ≤ 0.8 V
Input voltage range0 to 5.5 V
Output high≥ 4.4 V at −50 µA; ≥ 3.8 V at −8 mA
Output low≤ 0.1 V at 50 µA; ≤ 0.44 V at 8 mA
Quiescent supply current≤ 20 µA (inputs at VCC or GND)
Extra current per TTL-level input≤ 1.5 mA at 3.4 V in
Input capacitance10 pF maximum
A or B → Y delay5 ns typical / 8 ns max at 15 pF; 9 ns max at 50 pF
Input edge rate20 ns/V maximum

Specified at VCC = 4.5 V (dc levels) and 5 V ± 0.5 V (switching), 25 °C unless stated.

Four things that catch people out

The supply current is not zero when you hold a TTL level. Every input parked at around 3.4 V instead of at a rail adds up to 1.5 mA. Four gates with both inputs at 3.3 V can therefore draw several milliamps even when nothing is switching. That is normal for an HCT-type part, not a fault.

Never leave an input floating. Unused inputs must be tied to VCC or GND. A floating CMOS input drifts around the threshold and makes the gate oscillate and heat up.

Mind the output current limits. The recommended working current is 8 mA per output; 25 mA per output and 50 mA through VCC or GND are absolute maximum ratings, not design targets. Do not use the gate as an LED driver at full brightness.

A slow or noisy signal needs conditioning first. An AND gate has no hysteresis. If the incoming edge is slower than 20 ns per volt, clean it up with a Schmitt-trigger input such as the 74AC14 hex Schmitt-trigger inverter before it reaches the translator.

The exact stocked variant

iMania stocks Texas Instruments SN74AHCT08PWR. In TI’s part numbering, PW is the 14-pin TSSOP package (5.00 mm × 4.40 mm body) and R is the 2000-piece tape-and-reel carrier. It is a surface-mount part on a 0.65 mm pitch, so for breadboard work you will want a TSSOP-14 to DIP adapter board.

If you want the same function in through-hole and do not need level translation, the MC74HC08AN in PDIP-14 is the plain-HC equivalent – but remember that its inputs use the 0.7 × VCC rule described above and will not reliably accept 3.3 V signals at a 5 V supply.

Top view of the SN74AHCT08PWR TSSOP-14: pins 1 to 7 are 1A, 1B, 1Y, 2A, 2B, 2Y and GND; pins 14 down to 8 are VCC, 4B, 4A, 4Y, 3B, 3A and 3Y.
Top view. Pin 1 is marked by the dot or bevelled corner on the actual package.

The same TTL-threshold trick scaled up to eight bits is exactly what the SN74HCT541 octal bus buffer does, and when several sources must take turns on one wire you want 3-state outputs instead – see the SN74LS126A 3-state buffer guide.

View the SN74AHCT08PWR product page and availability.

Original data sheets: Texas Instruments SN54AHCT08, SN74AHCT08 (SCLS237P, October 2023). PDF. Threshold figures for plain HC logic from SN74HC08 (SCLS081J). PDF.