Retro computing field guide · Part 4

When to use a 74HCT541 bus buffer

The 74HC245 can pass eight bits either way. The 74HCT541 is different: it passes eight signals in one direction, and can disconnect its outputs when they should not drive the next bus.

See the SN74HCT541N

What does “buffer” mean here?

A buffer reads a logic level at an input and reproduces it at an output. In this chip, each A input has one matching Y output: A1 goes to Y1, and so on through A8 to Y8. The signals are non-inverting—a high input becomes a high output. The buffer adds a new output driver between two groups of wires; it is not memory and does not select an address by itself.

Eight signals flow from A inputs through the 74HCT541 to Y outputs only when both active-low output enables are low; either enable high disconnects the Y outputs
All eight channels share the same two enable inputs. Both must be low before the chip drives Y1–Y8.

Two enables, one direction

/OE1 low and /OE2 low

The outputs are enabled. Each Y output follows its A input after the chip’s propagation delay.

Either /OE input high

All eight Y outputs become high impedance (Hi-Z). The chip stops driving them; Hi-Z is not a logic zero.

No direction switch

Data flows A → Y only. Unlike the 74HC245, this chip cannot send data back from Y to A.

The slash means active low. The two enables apply to the entire eight-bit group, not four channels each. Both inputs need defined logic levels; do not leave either floating.

Pinout: inputs on one side, outputs on the other

Top-view 20-pin DIP SN74HCT541N pinout: pin 1 OE1, pins 2 through 9 A1 through A8, pin 10 ground, pins 11 through 18 Y8 through Y1, pin 19 OE2, pin 20 VCC
20-pin through-hole DIP, top view with the notch at the pin-1 end. The flow-through pinout places A inputs opposite Y outputs.

A write-only bus example

  1. Suppose a CPU-side eight-bit bus needs to send data to an output-only peripheral board. Connect the CPU-side signals to A1–A8 and the peripheral-side signals to Y1–Y8.
  2. Selection and write-control logic must enable the 541 only for the intended transaction. With /OE1 and /OE2 low, the byte appears on Y1–Y8.
  3. When either enable returns high, Y1–Y8 disconnect. The buffer does not remember the byte; the destination needs its own latch or register if it must retain the value.
Important limits. This is a conceptual path, not a complete 6502 schematic. A bidirectional CPU data bus also needs a return path for reads; the 541 alone cannot provide it. At a 4.5–5.5 V supply the HCT inputs use TTL-compatible thresholds, but the chip is not a general-purpose voltage-level translator. Check the source’s output levels, supply, output loading, timing and bus ownership for the exact circuit. Put a 0.1 µF bypass capacitor near VCC and GND.

The shop carries the SN74HCT541N in 20-pin DIP; check the live listing for current availability. If you have not met high-impedance outputs yet, start with the 74HC245 guide.