MM74HC165: read eight switches with three wires

What a shift register actually does

A shift register is a row of flip-flops in a chain. Each clock edge copies the value of one flip-flop into the next one, like people passing buckets down a line. The MM74HC165 has eight such stages, named QA through QH, and shifts data from QA towards QH.

What makes it a parallel-in register is the second way of getting data in. Instead of waiting eight clock edges, the chip can drop a value into all eight stages simultaneously, straight from eight input pins. That is the load operation, and it is the whole point of the part: you freeze eight signals at one instant and read them out at your leisure.

The three control pins

SHIFT/LOAD (pin 1) picks the mode. Hold it high and the chip shifts on clock edges. Pull it low and the eight parallel inputs are loaded straight into the register. The data sheet is explicit that this load happens independently of the state of the clock – it is asynchronous, so you do not have to line it up with anything.

CLOCK (pin 2) does the shifting. Data transfer occurs on the positive-going edge, that is, on the low-to-high transition.

CLOCK INHIBIT (pin 15) is a gate on the clock. Internally the two clock pins feed a 2-input NOR gate, so holding either of them high stops the register. If you only ever drive one clock source, tie CLOCK INHIBIT to ground and forget it.

One complete read, step by step

V_CC is pin 16, GND is pin 8, and a 100 nF capacitor belongs between them close to the chip. Connect eight switches to A–H (pins 11, 12, 13, 14, 3, 4, 5 and 6), each with a resistor to a defined level so no input ever floats.

1. Capture. With CLOCK low and CLOCK INHIBIT low, pulse SHIFT/LOAD low and back high. All eight switch states are now held inside the register. From this moment the switches may bounce or change freely – you are reading a snapshot.
2. Read the first bit without clocking. QH (pin 9) already carries the value loaded into the eighth stage, which came from input H (pin 6). This catches people out: if you clock first and read afterwards, you lose bit H and read a bit that was never there.
3. Shift seven times. Each rising edge on CLOCK moves the chain one place towards QH, so after the first edge QH shows G, then F, E, D, C, B and finally A (pin 11). Eight bits total: one free, seven clocked.
4. Repeat. Pulse SHIFT/LOAD low again for the next snapshot. The register does not need to be emptied first; loading overwrites all eight stages at once.

In other words, the byte arrives H first, A last – most-significant-bit first if you call H bit 7. If your code receives the switches mirrored, this is almost always why.

Reading it with SPI

The sequence above is exactly an SPI read with clock polarity 0 and phase 0, so most microcontrollers can do it in hardware: wire CLOCK to SCK, QH to MISO, and drive SHIFT/LOAD from a spare output pin. One byte transferred in, eight switches read. Nothing is ever sent to the chip, so MOSI stays unconnected.

Keep the clock inside the chip’s abilities: the data sheet quotes a typical clock-to-Q propagation delay of 20 ns, and its guaranteed limits are specified for supply voltages of 2 V, 4.5 V and 6 V. At 5 V a few megahertz is unremarkable; it is the wiring, not the chip, that usually sets the limit.

Chaining two registers for 16 inputs

Pin 10 is SERIAL INPUT. It feeds the first stage, QA – the far end of the chain from the output. Connect the QH output (pin 9) of one chip to the SERIAL INPUT (pin 10) of the next, share SHIFT/LOAD and CLOCK between them, and you have a 16-bit register read from one wire with sixteen clock edges. Add a third chip for 24 inputs; the only cost is time.

Pin 7 is the complementary output /QH – the same serial data inverted. It is useful when the receiving logic expects the opposite polarity, and harmless to leave unconnected.

The numbers that matter

Four things that catch people out

A 3.3 V microcontroller cannot reliably drive this chip at 5 V. Running on 4.5 V the data sheet only guarantees a high from 3.15 V, and at 5 V it wants roughly 3.5 V. The clean fix is to run the ’165 from 3.3 V as well, which is inside its 2–6 V range, or to translate the control lines – see the SN74AHCT08 level-shifting guide. Its serial output into a 3.3 V input needs the opposite direction, so do not mix supplies casually.

Never leave a parallel input floating. An unused A–H pin must be tied to V_CC or GND. A switch alone is not enough: it defines the level in only one of its two positions, so each switch needs a pull-up or pull-down resistor.

Change CLOCK INHIBIT only while CLOCK is high. Because both clock pins feed one NOR gate, a transition on CLOCK INHIBIT while CLOCK is low looks like a clock edge to the register and silently shifts your data one place.

Mechanical switches bounce. The register will happily capture a bounce as a real state change. Either sample slowly and compare consecutive reads in software, or clean the edges up in hardware with a Schmitt-trigger input such as the 74AC14 hex Schmitt-trigger inverter.

Where it fits among other registers

This part is deliberately one-directional: inputs in, serial out. When several devices must instead take turns driving one shared bus, you want 3-state outputs, as in the MC74HC173 4-bit 3-state register guide. When a whole byte has to move between a CPU and a bus in both directions, that is a transceiver’s job – see the 74HC245 guide. And if the eight bits you have just shifted in are meant to light a digit, the MC74HC4511 7-segment guide takes it from there.

In a bus-based machine such as a 6502 system, a shift register is usually the cheap alternative to decoding another address: no chip select, no timing window, just three ordinary output pins. The 74HC138 address-decoding guide covers the other approach, and the 6502 parts guide puts both in context.

The exact stocked variant

iMania stocks the MM74HC165MX. In Fairchild’s ordering code, M is package M16A, a 16-lead narrow-body SOIC to JEDEC MS-012 (0.150″ body), and the appended X marks tape-and-reel packaging. The reel label also carries customer code 099.200.052; the maker of this particular reel has not been independently verified, so compare the marking on the part itself before production use.

It is a surface-mount part on 1.27 mm pitch. That is hand-solderable with ordinary tools, but for breadboard work you will want a SOIC-16 to DIP adapter. The plain through-hole MM74HC165 in PDIP-16 is the same die in package N16E; it is a different order code and is not part of this lot.

View the MM74HC165MX product page and availability.

Original data sheet: Fairchild Semiconductor MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register, DS005316, September 1983, revised February 1999. Pin numbers, control behaviour, package codes and all figures above are taken from that document.