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A bus can only carry one value at a time, so anything that stores a value and later puts it back on the same wires needs two separate switches: one deciding when to remember, and one deciding when to speak. The MC74HC173N has both. It is four D flip-flops with a common clock, a pair of data-enable inputs and a pair of output-enable inputs that put the outputs into a high-impedance state.
A register is memory for one moment in time. Each of the four D flip-flops copies the level on its D input to its Q output on the rising edge of the common Clock (pin 7), and then holds that level until the next clock edge. The four data inputs are D0 (pin 14) through D3 (pin 11) and the four outputs are Q0 (pin 3) through Q3 (pin 6); note that this part numbers its bits from 0, which not every logic family does. That is the difference between this chip and a plain buffer: a 74HC245 bus transceiver and a 74HCT541 buffer pass data through and forget it, while this part keeps it after the source is gone.
Two pairs of enables keep the two jobs apart. DE1 (pin 9) and DE2 (pin 10) are the active-low Data Enable inputs: only when both are low does a rising clock edge load the D inputs into the flip-flops. If either one is high, the clock edge is ignored and the stored value does not change, so you can clock the whole bus continuously and still choose which register loads. OE1 (pin 1) and OE2 (pin 2) are the Output Enable inputs and work the other way round: if either one is high the Q outputs go to a high-impedance state and the chip releases the bus, and only when both are low do the outputs show what is stored. Reset (pin 15) is active high and asynchronous — it clears all four flip-flops without a clock edge, so a high level there forces the stored value to zero. Because DE and OE are independent, the chip can hold a value while invisible on the bus, which is exactly what makes several of them share one set of wires.
Here is one complete transaction on a shared 4-bit bus. Power the chip with VCC on pin 16 and GND on pin 8; the data sheet allows 2 to 6 V, so 5 V is typical. Start with Reset low, both OE high so the outputs are released, and both DE high so nothing loads. To write the value 1010, the sender drives the bus with D3=1, D2=0, D1=1, D0=0, then pulls DE1 and DE2 low. At 4.5 V the data sheet requires that data to be stable at least 20 ns before the clock edge and to stay for 3 ns after it. Give the Clock a rising edge — at least 16 ns wide at 4.5 V — and the four bits are now stored. Take DE1 and DE2 high again and the register ignores every later clock edge, so the sender can let go of the bus entirely. To read the value back, pull OE1 and OE2 low; within 30 ns at 4.5 V the outputs leave the high-impedance state and drive 1010 onto the same four wires. Take them high again and the bus is free for the next device. At 4.5 V the part is rated for a clock up to 30 MHz and at most 35 ns from the clock edge to a valid output.
The important rule on a shared bus is that exactly one device may drive it at a time. Two chips with their outputs enabled onto the same wire fight each other, waste current and produce an unpredictable level, so the output enables of everything on the bus must be mutually exclusive. A decoder is the usual way to arrange that: one output of a 74HC138 per device, so by construction only one is selected. If your source of data and address lines is a programmable peripheral chip such as the CA82C55A, the same discipline applies to its port directions. Two MC74HC173N side by side, sharing Clock and Reset but with separate DE pairs, give you an 8-bit register in which each half loads independently.
The figure shows the stocked N-suffix 16-pin plastic DIP from above, with pin 1 at the notch and numbering counter-clockwise. Pin 1 is OE1 and pin 2 is OE2; pins 3 to 6 are the outputs Q0 to Q3 in order; pin 7 is Clock and pin 8 is GND. On the other side pin 9 is DE1 and pin 10 is DE2, then the data inputs run backwards: pin 11 is D3, pin 12 is D2, pin 13 is D1 and pin 14 is D0. Pin 15 is Reset and pin 16 is VCC. Tie every unused input to GND or VCC rather than leaving it floating; a floating CMOS input drifts and draws current. In particular, if you only ever want the register enabled, tie the unused half of each enable pair low instead of leaving it open.
The data sheet states that this part is identical in pinout to the LS173, so it drops into an older TTL design, but the electrical side is not identical. Its inputs are made for standard CMOS output levels; to drive them from LSTTL outputs the data sheet asks for pull-up resistors, because an LSTTL high is not guaranteed to reach the CMOS input threshold. Going the other way is easier: the outputs are specified to drive 15 LSTTL loads and interface directly to CMOS, NMOS and TTL. The quiescent supply current is only 8 microamps per package at 6 V, so what it costs to run is dominated by how fast you clock it, not by the register itself.
See the MC74HC173N product.
Source: Motorola MC74HC173 technical data, Quad 3-State D Flip-Flop with Common Clock and Reset, in the High-Speed CMOS Logic Data book (DL129 Rev 6). Motorola PDF.
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