PhaseLatch v1.2 is an experimental, open-source ADC board designed to interface directly with classic MOS 6502-class CPUs and other retro computing systems. The board features a dual-channel 10-bit, 20 MSPS analog-to-digital converter with straight-binary parallel output, allowing ADC data to be memory-mapped directly onto a 6502 data bus for high-speed sampling experiments.
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Unlike typical SDR front-ends that rely on modern microcontrollers or FPGAs, PhaseLatch intentionally targets highly constrained 8-bit systems . This makes it a great platform for exploring bus timing, external memory expansion, and minimalist DSP techniques such as Goertzel tone detection running entirely on a vintage CPU.
Version 1.2 introduces several improvements over the initial revision, including corrected footprints, simplified power configuration, and integrated analog filtering to make the board easier to use in SDR and signal-processing experiments.
The board uses an Arduino-shield-style form factor and is designed to stack with the PhaseLoom IQ mixer and the 65uino system , enabling modular SDR experiments and retro-computing projects. While the ADC itself supports high sample rates, achievable throughput depends heavily on CPU clock speed, bus timing, and software implementation .
PhaseLatch can also be paired with external interfaces such as USB data bridges for high-speed streaming to modern SDR software , making it useful both for pure retro-CPU experiments and hybrid SDR development.
PhaseLatch is intended for experimentation, learning, and pushing vintage hardware beyond its original limits.
HW Source: https://github.com/AndersBNielsen/PhaseLatch
Software is part of the 65uino