SN74HC373N: store eight bits with a transparent latch

A processor can put eight bits on a data bus, but soon needs that bus for something else. The SN74HC373N can hold those bits at its outputs. This guide explains a transparent latch and how to write a byte without letting two devices drive the same bus.

The basics: transparent or stored

A latch stores one bit. While LE (latch enable) is HIGH, it is transparent: each Q output follows its corresponding D input. When LE goes LOW, the last value is stored and Q keeps it even if D changes. This chip has eight channels, 1D–8D and 1Q–8Q; its channel numbers are not 0–7.

What does OE do?

OE on pin 1 is active LOW. With OE LOW, stored values appear at Q. With OE HIGH, every Q output is high impedance (3-state): it releases the connection without erasing the stored bits. Several devices can thus share a bus, provided no more than one enables its outputs at once.

Top-view pinout

SN74HC373N 20-pin PDIP, top view with notch at the top. The slash before OE means active LOW.
SN74HC373N 20-pin PDIP, top view with notch at the top. The slash before OE means active LOW.

One complete byte write

Suppose a 5 V controller wants to store 10100101 on outputs 8Q…1Q. Start with OE HIGH so the outputs do not drive the shared bus.

  1. Keep LE LOW and set 8D…1D to 10100101. The stored word does not change yet.
  2. Raise LE. The latch opens and its eight internal bits follow D. Keep data stable before lowering LE.
  3. Lower LE. Now 10100101 is stored; D can change without altering the stored bits.
  4. Once the bus is free, lower OE: 8Q…1Q drive 10100101. Raise OE before another device is allowed to drive the bus.
One write cycle: open the latch with LE HIGH, present data, close it with LE LOW; OE separately decides whether Q drives the bus.
One write cycle: open the latch with LE HIGH, present data, close it with LE LOW; OE separately decides whether Q drives the bus.

Try it on a breadboard

For a standalone test: place the PDIP-20 across a breadboard centre gap. Connect pin 20 to regulated +5 V, pin 10 to GND, and a 100 nF ceramic capacitor close between them. Give each D input its own 10 kΩ pull-down to GND and a switch to +5 V. Give LE and OE defined levels with 10 kΩ resistors; switches can change the levels. Connect one Q output to an LED with a 2.2 kΩ series resistor to GND. Repeat for other Q pins only after checking total output loading. This is a local demonstration, not a complete bus interface.

Electrical limits and pitfalls

Do not assume that an unbuffered 3.3 V output is guaranteed HIGH when the HC chip runs at 5 V: the guaranteed HC HIGH input threshold at 4.5 V supply is 3.15 V, leaving little margin that must be checked against the controller. Never feed a 5 V Q output directly into a non-5 V-tolerant input. A suitable HCT input or level shifter may be needed for mixed 3.3/5 V systems. Never leave CMOS inputs floating, and observe the datasheet setup, hold and pulse-width requirements at speed. OE is not a reset; power-up contents are unknown until you write a value.

Related guides

To hold four bits on a shared bus instead, see the MC74HC173 register guide. For moving a bus between systems, see the 74HC245 bus transceiver guide.

Product and source

The stocked part is Texas Instruments SN74HC373N in a 20-pin PDIP (N). Pinout, LE/OE behaviour and limits were checked against TI datasheet SCLS140G.

View the SN74HC373N product · Read the TI datasheet